Analog Layout Engineer
Core
Analog layout designer providing onsite support for advanced nodes, working with global layout and design team.
Role type
Senior Analog Layout Engineer
Builds
Block level and IP level Analog layout designs for SerDes, ADC/DAC, PLL, and top-level integration
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, Floorplanning, DRC/LVS debugging, Antenna error resolution, ESD/Latch-up/EM analysis, Deep sub-micron process knowledge, Cadence tools, TSMC processes
Preferred skills
FinFet experience, RF layout experience
Technologies
Cadence, TSMC
Responsibilities
Work independently on block level and IP level Analog layout design, Coordinate with circuit designer and layout team, Handle top-level integration, Debug complex issues involving DRC, LVS, and antenna errors, Determine methods and procedures for new assignments
Seniority
Senior, hands-on IC