Design Engineer - STA
Core
Chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies (3nm and smaller) for AI, computing, and networking SoCs.
Role type
Senior IC Static Timing Analysis (STA) Engineer
Builds
High-performance System-on-Chip (SoC) designs operating at speeds exceeding 1 GHz
Domain
Semiconductor / VLSI Design / ASIC Physical Design
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), timing constraint creation, multi-mode multi-corner (MMMC) timing, ECO convergence, signal integrity analysis, clock network design, Tcl scripting, Linux/UNIX environments
Preferred skills
Python/Perl/Ruby scripting, Synopsys PrimeTime or Cadence Tempus, POCV/SOCV/LVF techniques, PBA, SPICE correlation, timing library knowledge (CCS/ECSM/NLDM)
Technologies
Synopsys PrimeTime, Cadence Tempus, Tcl, Python, Perl, Ruby, Linux, UNIX
Responsibilities
Develop and validate timing constraints across multiple modes and corners; Perform pre- and post-route timing analysis and closure verification; Generate and validate timing ECOs; Automate timing flows using scripting; Analyze and debug timing violations and clock network challenges; Collaborate with physical design, synthesis, and clock teams.
Seniority
Senior, hands-on IC
