Analog Layout Design Engineer
Core
Leading FPGA physical design and layout of complex digital, analog, and mixed-signal integrated circuits (ICs) to ensure optimal performance, reliability, and manufacturability.
Role type
Senior Analog Layout Design Engineer
Builds
Complex digital, analog, and mixed-signal integrated circuits (ICs)
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/mixed-signal IC layout design, Floorplanning, Placement, Routing, Physical verification (DRC, LVS, ERC, RV), EDA tool proficiency (Cadence Virtuoso, Mentor Graphics), Transistor-level circuit topology understanding, Process design rule compliance
Preferred skills
Team leadership, Mentoring junior engineers
Technologies
Cadence Virtuoso, Mentor Graphics
Responsibilities
Lead and execute layout design of digital, analog, and mixed-signal circuits; Collaborate with circuit designers on requirements and constraints; Plan and manage layout schedules and resources; Perform floorplanning, placement, and routing optimization; Conduct physical verification (DRC, LVS, ERC, RV); Drive design reviews and mentor junior engineers; Interface with foundry partners for compliance; Document design methodology and layout guidelines
Seniority
Senior, hands-on IC design with leadership responsibilities
