Design Engineer - STA
Core
Design Engineer specializing in Static Timing Analysis (STA) for VLSI and ASIC physical design, ensuring timing integrity across complex digital circuits.
Role type
Senior IC Design Engineer (STA)
Builds
High-performance ASIC/VLSI chips with verified timing constraints
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features
Required skills
VLSI and ASIC physical design, Static Timing Analysis (STA), Synopsys PrimeTime, Cadence Tempus, TCL scripting, RC network analysis, Signal Integrity, Setup/Hold analysis, Timing diagram creation
Preferred skills
POCV/SOCV/LVF modeling, Multi-input switching (MIS), Liberty timing models (CCS/ECSM/NLDM), Path-based analysis (PBA), Location-aware timing derates (LOCV/SOCV), 3DIC design experience, SPICE analysis, Python/Ruby/BASH
Technologies
Synopsys PrimeTime, Cadence Tempus, SPICE
Responsibilities
Create and debug timing constraints, analyze and debug timing tool warnings/errors, generate and interpret timing reports, model process/voltage/temperature variations, collaborate with cross-functional teams across time zones
Seniority
Senior, hands-on IC
