Principal Physical Design Engineer
Core
Delivering TFM (tool, flow and methodology) for Physical Design tasks at block, sub-chip, and full-chip levels, including PnR, STA, PV, and FEV.
Role type
Principal Physical Design Engineer
Builds
ASICs and SoCs
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Place and Route (PnR), Static Timing Analysis (STA), Physical Verification (PV), Formal Equivalency Verification (FEV), Global Clocking Construction, IR-Drop/EM analysis, IP collateral handling, TCL scripting, Python scripting
Preferred skills
Experience with leading-edge technology tapeouts, expertise in Synopsys Fusion Compiler/PrimeClosure/Primetime/Star-RC, expertise in Cadence Innovus, expertise in Siemens Calibre, understanding of foundry tech files and rule decks
Technologies
Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, Cadence Innovus, Siemens Calibre
Responsibilities
Lead PnR convergence recipe development for blocks/subsystems, develop methodologies to improve physical design efficiency, sign off blocks on timing and verification, implement functional and timing ECOs, design global clocking schemes, conduct physical design reviews and resolve issues
Seniority
Principal, hands-on IC with strategy & mentorship