Principal Engineer
Core
Lead ASIC design and implementation for 5nm/3nm CMOS cell-based solutions, managing the full development lifecycle from RTL analysis to post-prototype test support.
Role type
Principal IC Design Engineer (ASIC)
Builds
High-performance ASIC chips for internal and external customers
Domain
Semiconductor / VLSI / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full chip synthesis (DC, DCT, DCG), Static Timing Analysis (STA), Physical Design (floor planning, placement, design closure), DRC & LVS, RTL analysis, design optimization, timing verification, simulation, test insertion, vector generation, post-prototype test support
Preferred skills
DFT insertion, Power/IVD analysis, Top Floorplan/STA & Low Power
Technologies
5nm/3nm CMOS, Perl, Tcl, Python
Responsibilities
Execute full chip synthesis and STA flows for tape-out; perform physical design implementation including floor planning and design closure; handle block implementation and top-level tasks independently; support RTL analysis, simulation, and test insertion; collaborate with internal and external customers on state-of-the-art IC solutions.
Seniority
Principal, hands-on IC