R&D Digital Design Engineer
Core
Verification of cutting edge network switch routing designs (L2/L3) for Tomahawk ASICs supporting Scale-Out and Scale-Up AI Networks.
Role type
Senior IC digital design verification engineer (ASIC/SOC)
Builds
Tomahawk ASICs for high-volume traffic networking solutions
Domain
Networking hardware / ASIC design / AI infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Perl, Python, OOP, L2/L3 networking protocols, traffic management, scheduling, shaping, latency characterization, test plan definition, coverage closure
Preferred skills
Experience with mass production ASIC/SOC silicon, modular reusable verification environments
Technologies
Systemverilog, UVM, Perl, Python, Makefiles
Responsibilities
Develop verification environments including testbenches and verification APIs; Implement test plans into executable test suites; Execute verification processes pre-silicon using functional and code coverage metrics; Understand chip architecture to create in-depth test plans for key networking features
Seniority
Senior, hands-on IC
