ASIC Verification Engineer
Core
Architect and develop block-level verification environments for sub-system and full-chip ASICs using SystemVerilog and UVM methodology to enable faster, denser, feature-rich systems.
Role type
ASIC Verification Engineer
Builds
ASIC verification suites and tests for networking hardware
Domain
Networking hardware / ASIC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, constrained-random verification, Perl/Tcl scripting, ASIC debugging, logic design collaboration, functional coverage analysis, gate-level simulation
Preferred skills
OVM/VMM methodology, Ethernet protocol verification
Technologies
SystemVerilog, UVM, VCS, Xcelium, Perl, Python, Shell
Responsibilities
Architect and develop block-level verification environments for sub-system and full-chip using System Verilog and UVM methodology; Define, architect, code, and deliver verification suites/tests for ASICs; Verify large ASIC blocks independently and sign off for tape-out with analysis of code and functional coverage; Work closely with logic designers to resolve bugs and assist software developers in bring-up development; Develop Perl, Python, and/or shell scripts to improve verification infrastructure.
Seniority
Mid-level IC (3+ years experience)
