Senior Silicon Engineer

United States, Washington, Redmond💼 Full-time🗓 2026-07-20 → 2026-07-31

Core

Validating silicon to solve complex problems in a datacenter by developing programmable silicon implementations and verifying complex flows at SOC, subsystem, or IP levels.

Role type

Senior IC ASIC verification engineer (Data Processing Unit)

Builds

Programmable silicon implementations for datacenter applications

Domain

Semiconductor / Data Processing Units / Networking

Deliverable

Required skills

UVM/C verification methodology, RTL verification, SoC verification, processor architecture knowledge, peripheral interconnect bus protocols, Verilog, System Verilog, random-stimulus techniques, coverage-based techniques, stress and performance scenario creation

Preferred skills

Ethernet, TCP/IP, MAC/PCS, Networking blocks

Technologies

UVM, C, Verilog, System Verilog

Responsibilities

Develop verification environments and run/debug simulations, define verification strategies and test plans, apply random-stimulus and coverage-based techniques to find bugs, create stress and performance scenarios, perform pre-silicon verification and post-silicon validation

Seniority

Senior, hands-on IC

Rewrite

## About the role As a Senior Silicon Engineer - ASIC verification in the Data Processing Unit team you will be validating silicon to solve complex problems in a datacenter. You will interact with the architecture team to develop a programmable silicon implementation. This position is expected to be highly visible and impactful. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career. As a Senior Silicon Engineer in the Data Processing Unit team, you will be validating silicon to solve complex problems in a datacenter. ## Requirements - Own verification of complex flows at the SOC, subsystem, or IP levels using UVM/C test bench - Learn about the design and interact with partner teams to define verification strategies and test plans - Develop verification environments and run and debug simulations to drive quality - Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals - Running tests, debugging failures, creating stress and performance scenarios to meet test plan goals - Perform pre-silicon verification, post-silicon validation by defining testing strategies ## Nice to have - Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience - Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience - Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience - Equivalent experience - 5+ years of RTL Verification using UVM/C verification methodology - Knowledge of Ethernet, TCP/IP, MAC/PCS, Networking blocks - Proven track record with the Verification and development of complex SoCs. - In depth understanding of processors and peripheral interconnect bus protocols and architectures - Strong knowledge of Verilog, System Verilog, UVM methodology - Self-motivated and able to work effectively both independently and in a team.

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