R&D Engineer Adv Tech Dev (PKE) / Sr. Staff
Core
Lead IC packaging engineering for advanced silicon nodes (5nm, 3nm, 2nm), defining custom package solutions, materials, and processes to meet signal integrity, power integrity, and thermal requirements.
Role type
Sr. Staff IC Packaging Engineer
Builds
Custom IC packages and advanced assembly processes for cutting-edge silicon products
Domain
Semiconductor manufacturing, advanced node chip packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Signal integrity (SI) and power integrity (PI) analysis, advanced assembly processes (flipchip, MCM, 2.5D), Chip Packaging Interaction (CPI) materials expertise, failure analysis techniques, GD&T and mechanical drawing interpretation, project management, substrate manufacturing knowledge
Preferred skills
Journal publications or patent awards, knowledge of 2.5D/3DIC/glass substrate technologies, innovation track record
Technologies
Cadence APD, ELK, MiM structures, SAP/mSAP, PSPI w/ Cu RDL
Responsibilities
Design custom packages with IC/system design and thermal teams; research and productize new materials (TIM, underfill); manage packaging from concept to high-volume production; troubleshoot packaging issues; create design documentation and assembly instructions; interface with suppliers and customers for NPI and quality resolution
Seniority
Sr. Staff, hands-on IC with strategic team impact
