IC Package Engineer
Core
Designing substrate layouts and IC packages for advanced AI chips to ensure mechanical and electrical integrity for high-performance hardware.
Role type
IC Package Design Engineer
Builds
AI chips (ASICs) with model-specific architectures
Domain
Semiconductor / Advanced Packaging / AI Hardware
Deliverable
production ML models
Required skills
CoWoS design, large-scale BGA design (>4000 balls), substrate layout, package warpage mitigation, mechanical stress analysis, design validation, reliability testing (thermal, shock, shear, HAST, ALT), 2.5D/3D stacking knowledge, thermal management techniques
Preferred skills
Experience with >20Ghz signaling and >500W power, stiffener design, open vs. closed package requirements, familiarity with Cadence APD/SIP or Mentor Xpedition
Technologies
CoWoS, BGA, Cadence APD/SIP, Mentor Xpedition
Responsibilities
Own end-to-end package design process including substrate layout and IC package design, conduct mechanical and warpage analysis, perform design validation against electrical and mechanical constraints, oversee package reliability testing, collaborate cross-functionally with chip design, thermal, mechanical, and manufacturing teams
Seniority
Mid-Senior, hands-on IC
