Principal Engineer, Signal-Integrity and Power-Integrity
Core
Lead the design, analysis, and validation of next-generation advanced packaging solutions for HBM and logic-memory integration, ensuring signal and power integrity across the full stack.
Role type
Principal Engineer (Signal-Integrity and Power-Integrity)
Builds
High-performance SiP architectures (HBM, interposer, 3D stacks) and advanced packaging solutions
Domain
Semiconductor / Advanced Packaging / High-Speed Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SIPI engineering, 2.5D/3D package architectures, HBM, interposer, TSV, high-speed I/O standards, power-delivery networks, electromagnetic extraction, multi-port S-parameter analysis, power-network optimization, tape-out sign-off, cross-functional leadership, technical mentorship
Preferred skills
2.5D/3D packaging for HBM/GPU-memory, PDN impedance profiling, IBIS model validation, PCIe Gen5/Gen6/CXL/UCIe/JEDEC standards, advanced packaging workflows, scripting/automation (Python/TCL/SKILL), high-speed interface validation, technical publications
Technologies
Ansys SIwave/RedHawk, Cadence Sigrity, oscilloscopes, VNAs, compliance test platforms
Responsibilities
Define and own the SIPI roadmap for advanced PKG families; Lead the creation of high-performance SiP architectures and validate power/signal integrity; Invent and propagate best-practice SIPI methodologies; Oversee the end-to-end design flow (package definition, simulation, layout sign-off, tape-out); Coach senior and junior engineers; Conduct risk assessments and deliver final SIPI sign-off packages
Seniority
Principal, strategy & mentorship
