Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture
Core
Chief visionary and architect of the physical implementation backbone for next-generation, high-frequency CPU cores, pioneering AI-native automated methodologies for sub-3nm nodes.
Role type
Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture
Builds
High-frequency CPU cores for AI, machine learning, automotive, data center, mobile, and consumer applications.
Domain
Semiconductor chip design, VLSI, sub-3nm process nodes (N3/N2), AI/ML-driven EDA.
Deliverable
production ML models | product features
Required skills
Physical Design Methodology, RTL-to-GDS flow architecture, sub-3nm device physics, Synopsys Fusion Design Platform (IC Compiler II, PrimeTime), AI/ML EDA integration (DSO.ai, Cerebrus), hierarchical floor planning, timing closure, Python/Tcl/Perl automation, technical mentorship.
Preferred skills
TSMC N2/A14 node exposure, custom tool feature development, standard cell/SRAM library co-optimization.
Technologies
Synopsys Fusion Compiler, Synopsys IC Compiler II, Synopsys PrimeTime, Synopsys DSO.ai, Cerebrus, Python, Tcl, Perl.
Responsibilities
Architect and mandate RTL-to-GDS roadmaps for ultra-high-frequency CPUs; drive early-stage PPA modeling to influence micro-architectural decisions; lead integration of AI/ML EDA platforms for design space optimization; serve as technical authority with tier-one EDA partners; dictate global floor planning and timing budgeting for multi-million gate designs; establish scalable automation frameworks and build systems; mentor Principal and Senior engineers.
Seniority
Senior, hands-on IC with strategic leadership and mentorship.
