Staff Physical Design Engineer: CPU Implementation & Flow Automation

SiFive

Bengaluru, Karnataka, India💼 Full-time🗓 2026-09-28 → 2026-09-29

Core

Developing and perfecting RTL-to-GDS implementation flows for high-performance CPU cores on leading-edge process nodes.

Role type

Staff Physical Design Engineer (CPU Implementation & Flow Automation)

Builds

High-performance CPU cores for data-intensive applications

Domain

Semiconductor / CPU Design / Physical Implementation

Deliverable

production ML models

Required skills

RTL-to-GDS flow development, PPA optimization, ML-enhanced design automation, Synopsys Fusion Compiler, hierarchical physical design, Tcl/Python scripting, FinFET node expertise

Preferred skills

N2/GAAFET process knowledge, SRAM/Std Cell IP collaboration, complex timing/congestion resolution

Technologies

Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC, DSO.ai

Responsibilities

Develop and validate production-ready RTL-to-GDS recipes; Drive block-level and hierarchical PPA closure; Deploy ML tools for design space exploration; Resolve flow and tool-related bottlenecks; Partner with IP teams for PPA characterization; Create Tcl/Python scripts for flow automation

Seniority

Staff, hands-on IC with strategic flow ownership

Sourced via workday · Listed on CareerPlan, which tracks 854,000+ jobs from 20+ sources.

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.