Principal CPU Physical Design Engineer (San Diego, CA)
Core
Drive silicon success for next-generation CPU cores by owning implementation from RTL to GDS, optimizing timing, power, and area, and solving hard physical design problems at advanced nodes.
Role type
Principal CPU Physical Design Engineer
Builds
High-performance CPU cores for mobile and computing devices
Domain
Semiconductor / CPU Physical Design
Required skills
ASIC/SoC Physical Design, RTL-to-GDSII implementation, Timing closure, Power optimization, Scripting (TCL/Python), EDA tools (Synopsys/Cadence)
Preferred skills
CPU core experience, Advanced nodes (7nm/5nm/3nm), PPA trade-offs, Design methodologies, Data-driven debug
Technologies
Synopsys, Cadence, TCL, Python
Responsibilities
Own critical portions of CPU implementation from RTL to GDS, Drive timing/power/area optimization for high-frequency subsystems, Partner with Architecture/RTL/Circuit teams, Solve hard silicon problems (congestion, variability, EM/IR), Develop automation flows, Mentor junior engineers
Seniority
Principal, hands-on IC with mentorship
