Principal Engineer, Physical Design
Core
Architect and lead the development of next-generation physical design methodologies and automation flows for high-performance processor chips in leading-edge CMOS processes.
Role type
Principal Engineer, Physical Design (IC Design)
Builds
Next-generation server, 5G/6G, automotive, and networking processor chips
Domain
Semiconductor / IC Physical Design
Required skills
RTL-to-GDSII implementation, synthesis, floorplanning, place and route, clock tree synthesis, timing closure, static timing analysis, power/signal integrity analysis, scripting (Python, Perl, Tcl, Makefile), EDA tool evaluation
Preferred skills
EDA vendor experience, emerging technology adoption
Technologies
PrimeTime, Tempus, Voltus, RedHawk
Responsibilities
Architect physical design methodologies, provide technical leadership in RTL-to-GDSII flows, advise on design decisions, collaborate with cross-functional teams, mentor engineers, evaluate EDA tools, represent team in strategic discussions
Seniority
Principal, hands-on IC with strategic influence
