Physical Design CPU Methodology Engineer
Core
Define and drive implementation methodology, automation strategy, and signoff infrastructure for high-performance CPU cores across advanced process nodes.
Role type
Senior IC physical design methodology engineer (CPU)
Builds
High-performance RISC-V CPU cores and scalable physical design flows
Domain
Semiconductor / CPU Physical Design / AI/ML-enabled EDA
Deliverable
production ML models | product features
Required skills
RTL-to-GDS implementation, timing closure, power optimization, signal integrity (SI), electromigration/IR drop (EM/IR), physical verification, Tcl/Python/Perl scripting, technical leadership, cross-team influence
Preferred skills
AI/ML-enabled PD tooling, synthesis and PnR of CPU partitions, data-driven flow tuning
Technologies
Tcl, Python, Perl, advanced process nodes, EDA tools
Responsibilities
Define scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification; Develop AI/ML-enabled PD tooling and new program RM flow; Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows; Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams
Seniority
Senior, hands-on IC with technical leadership