SoC Physical Designer
Core
Graduate Physical Design Engineer developing advanced semiconductor products through complete physical implementation flow from netlist to GDSII.
Role type
Graduate IC physical design engineer
Builds
SoC and subsystem physical designs
Domain
Semiconductor / VLSI
Required skills
VLSI design flow knowledge, Linux/Unix environment usage, Python/Tcl/Perl/Shell/C++ programming, timing analysis, power analysis, signal integrity analysis, physical verification, EDA automation scripting, cross-functional collaboration
Preferred skills
ASIC/SoC design experience, Physical Design experience, Timing Analysis experience, DFT experience, Digital IC Design experience, Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, Tempus, Calibre, Machine learning/AI in semiconductor design
Technologies
Python, Tcl, Perl, Shell, C/C++, Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, Tempus, Calibre
Responsibilities
Support SoC and subsystem physical design implementation from netlist to GDSII, Perform timing, power, signal integrity, and physical verification analysis, Debug design implementation issues and drive convergence toward project PPAC targets, Develop and improve EDA automation scripts, Support silicon bring-up, design reviews, and tapeout activities, Contribute to continuous improvement of backend methodologies, flows, and best practices
Seniority
Graduate (Master's degree graduating in 2027)
