Junior Physical Design Engineer - MCU
Core
Execute RTL-to-GDSII physical implementation flow for complex SoC/MCU designs on advanced nodes to meet performance, power, and area targets.
Role type
Junior IC physical design engineer
Builds
Microcontroller units (MCUs) and System-on-Chip (SoC) designs for industrial automation and edge processing
Domain
Semiconductor / VLSI / Microelectronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII flow, floorplanning, power grid design, Place & Route (P&R), Clock-Tree Synthesis (CTS), physical verification (DRC, LVS, ERC, Antenna), static timing analysis (STA), timing constraints management, IR-drop analysis, Electromigration (EM) analysis, TCL/Python/Perl scripting, EDA tool troubleshooting
Preferred skills
Synopsys Fusion Compiler/ICC2/Formality, Cadence Innovus/Genus, Ansys RedHawk/Cadence Voltus, UPF/CPF low-power techniques, full-custom layout fundamentals, AI/ML in EDA
Technologies
Synopsys Fusion Compiler, ICC2, Formality, Cadence Innovus, Genus, Ansys RedHawk, Voltus, TCL, Python, Perl
Responsibilities
Support SOC-level floorplanning, power grid design, IO placement, Place & Route (P&R), Clock-Tree Synthesis (CTS) and physical verification (DRC, LVS, ERC, Antenna); Assist with tool setup, static timing analysis (STA), basic timing constraints management, IR-drop, and Electromigration (EM) analysis; Maintain and extend automation scripts (TCL, Python, Perl) to improve flow efficiency and design analysis
Seniority
Junior, hands-on IC
