Lead STA Engineer
Core
Lead static timing analysis (STA) for complex semiconductor ASIC/SoC designs to ensure timing closure and performance targets.
Role type
Lead STA Engineer
Builds
High-quality semiconductor chips (ASIC/SoC)
Domain
Semiconductor / Digital IC Design
Required skills
Static timing analysis (STA), Multi-mode timing constraint development, Timing signoff, Digital design fundamentals, Clocking architectures, Low-power techniques, Timing constraints (SDC), Scripting (Perl, Python, TCL), EDA tool automation, IP level synthesis
Preferred skills
Leading teams, Cross-functional collaboration
Technologies
Synopsys PrimeTime, Cadence Tempus, SDC, Perl, Python, TCL
Responsibilities
Create and validate Synopsys Design Constraints (SDC) for block and full-chip levels; Perform exhaustive timing analysis across multiple corners and modes (MCMM); Debug and resolve setup, hold, transition, and path-based violations; Drive timing closure by generating and evaluating Engineering Change Orders (ECOs); Partner with RTL, physical design, and DFT teams; Develop and support implementation flows using EDA tools; Lead a small team of STA engineers; Perform IP level synthesis.
Seniority
Senior, hands-on IC lead
