Principal Layout Engineer
Core
Lead block-level and top-level analog/mixed-signal layouts for custom silicon solutions serving consumer and automotive applications.
Role type
Principal Analog Layout Engineer (Layout Lead)
Builds
Custom analog-on-top and digital-on-top mixed-signal ICs
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (ICs)
Required skills
Deep sub-micron CMOS layout, Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, PVS DRC/LVS/ERC, Matching techniques, Common centroid, Shielding, EM/IR analysis, High-speed routing, Parasitics extraction, DFM practices, Analog-on-top/Digital-on-top integration, Power distribution, Multiple voltage domains, PLL/OSC/ADC/DAC/LDO/Bandgap circuit layout
Preferred skills
SKILL scripting, Perl scripting
Technologies
Cadence Virtuoso XL, PVS, SKILL, Perl
Responsibilities
Develop and lead block-level and top-level analog/mixed-signal layouts; Drive floorplanning, power routing, ESD implementation, and chip integration; Run and debug DRC, LVS, ERC, and extraction flows; Collaborate with design, digital P&R, IO, ESD, package, test, and PDK teams; Identify layout risks and drive resolution of design and PDK issues; Improve layout methodologies and automation.
Seniority
Principal, hands-on IC design with technical leadership
