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Senior Analog IC Layout Engineer

Seoul (Jung-gu)💼 Full-time🗓 2026-07-20 → 2026-07-31

Core

Lead physical implementation of complex automotive mixed-signal and power management integrated circuits from planning through tape-out.

Role type

Senior Analog IC Layout Engineer

Builds

Advanced automotive and industrial semiconductor products

Domain

Automotive Power Solutions / Mixed-Signal IC Design

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

Analog IC Layout development, Cadence Virtuoso, DRC/LVS sign-off methodologies, CMOS/BCD/SOI design environments, Floorplanning, Tape-out execution

Preferred skills

Calibre/PVS/Quantus/StarRC, High Voltage technologies, Layout automation scripting (SKILL/Python/TCL/Shell), Multi-site international R&D experience, AI-assisted engineering tools

Technologies

Cadence Virtuoso, Calibre, PVS, Quantus, StarRC, SKILL, Python, TCL, Shell

Responsibilities

Lead physical implementation of Analog and Mixed-Signal integrated circuits, Define and optimize floorplans for complex blocks and top-level assemblies, Drive layout activities from planning through tape-out, Own DRC, LVS, ERC and physical sign-off activities, Support extraction analysis and post-layout verification, Coordinate layout activities with Design, Verification, Package, Test and Product Engineering teams

Seniority

Senior, hands-on IC with mentorship

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