Senior DfT Engineer
Core
Design and implement Design for Test (DfT) architectures for complex analog, mixed-signal, and digital chips to ensure testability and debuggability.
Role type
Senior DfT Engineer (IC)
Builds
Production silicon chips with embedded DfT infrastructure
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design (Verilog, System-Verilog), DfT architecture, Scan insertion, ATPG, Debug, Mixed-signal IP knowledge, Digital logic design
Preferred skills
Experience with standard Macros (RAM, ROM, NVM, ADC, DAC), P&R-aware rerouting, Chiptop level DV environment
Technologies
Verilog, System-Verilog, ATPG tools, Simulation environments
Responsibilities
Collaborate with design leads to define testability requirements, design DfT for analog/digital IPs, write verification tests and debug, optimize scan chains and insert test points, support silicon debug, generate DfT documentation, troubleshoot DfT issues
Seniority
Senior, hands-on IC
