DFT Engineer
Core
Designing and implementing Design for Testability (DFT) architectures and flows for next-generation AI silicon chips targeted at data center applications.
Role type
Senior IC DFT Engineer
Builds
Next-generation AI silicon designs for data centers
Domain
Semiconductor / AI Compute / Digital Integrated Circuits
Deliverable
production ML models
Required skills
DFT methodologies (JTAG, IJTAG, Core Test, SSN, Test Compression, OCC), MBIST/BISR implementation, ATPG tools, Verilog/SystemVerilog, STA constraints, Python/TCL/Perl/Shell scripting, gate-level simulation, silicon bring-up testing
Preferred skills
Scan-based testing, pre-silicon DFT verification, post-silicon tester pattern debugging
Technologies
Synopsys VCS, Synopsys Verdi, IEEE 1149.x, IEEE P1687, IEEE P1500
Responsibilities
Define and implement DFT architecture and features for AI designs; Develop efficient DFT flows compatible with silicon design flows; Generate structural test vectors and analyze test coverage; Integrate DFT requirements with design, verification, and physical design teams; Support silicon bring-up and identify failures to enhance yield.
Seniority
Senior, hands-on IC
