Director - STA
Core
Managing a team of engineers to perform Static Timing Analysis (STA) and ensure timing closure for complex AI, Edge, and Automotive Processors (MPUs) at advanced nodes.
Role type
Senior IC Static Timing Design Manager
Builds
World-class MPUs and complex SoCs for AI, Edge, and Automotive applications
Domain
Semiconductor Physical Design / SoC Implementation
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), Physical Design, Floor-planning, Place & Route, Timing closure, Constraint generation and verification, Verilog, RTL collaboration, Cross-functional team leadership, Methodology improvement
Preferred skills
AI and agents in STA & PD domains, Deep understanding of crosstalk, noise, OCV, timing margins, Clock specs, jitter, IR drop, spice analysis
Technologies
EDA vendors, DTCO tools
Responsibilities
Develop, implement, and verify STA constraints; Coordinate with global design teams (RTL, DV, DFT) to complete large SoC projects; Influence early design decisions with Architecture and RTL teams; Lead methodology improvements for timing flows
Seniority
Senior, hands-on IC with team management
