Senior Hardware Verification Engineer
Core
End-to-end functional verification of complex digital designs (IP, Subsystem, or SoC) using UVM-based testbenches to ensure architectural specifications are met before tape-out.
Role type
Senior IC hardware verification engineer (ASIC)
Builds
Production ASIC chips (IP, Subsystem, SoC)
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random stimulus, formal verification, hardware emulation, waveform analysis, functional coverage modeling, power-aware verification (UPF/CPF), technical leadership
Preferred skills
Experience with VPD/FSDB, JasperGold, VC Formal, Palladium, Zebu
Technologies
SystemVerilog, UVM, JasperGold, VC Formal, Palladium, Zebu, VPD, FSDB, UPF, CPF
Responsibilities
Define verification plans (vPlan) including test scenarios and coverage models; Architect scalable verification environments; Develop constrained-random and directed tests; Root-cause hardware failures via waveform analysis; Drive functional and code coverage to 100%; Verify throughput, latency, and power-aware features; Integrate formal verification and hardware emulation; Mentor junior engineers and perform code reviews.
