STA Engineer
Core
Drive subsystem-level static timing analysis (STA) and timing closure for complex SoCs, sub-systems, and cores across pre-layout and post-layout phases.
Role type
Senior IC STA and Synthesis Engineer
Builds
Next-generation connectivity chipsets for mobile, access point, XR, automotive, and IoT platforms
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), timing constraint development, synthesis (low-power flows), logical equivalence checking, multi-mode multi-corner timing closure, OCV/AOCV/POCV, RTL-to-netlist/netlist-to-netlist verification, SoC clocking and reset architecture, scripting (TCL, Perl, Python), low-power implementation (UPF, multi-voltage), AI-driven automation flows
Preferred skills
Experience with Synopsys PrimeTime, Synopsys Design Compiler, or Cadence Genus
Technologies
PrimeTime, Design Compiler, Genus, TCL, Perl, Python, UPF
Responsibilities
Perform timing analysis using PrimeTime or equivalent tools and contribute to full-chip signoff; identify timing issues, investigate violations, and recommend micro-architectural or implementation-level improvements; develop and validate SDC constraints for accurate STA execution; define and manage I/O timing budgets across hierarchical designs; provide timing guidance at block, sub-system, and full-chip levels including root cause analysis and ECO support; manage large-scale multi-corner and multi-mode STA runs through automation; collaborate with RTL, synthesis, and physical design teams to achieve robust timing closure; perform synthesis, low-power synthesis, formal verification, and low-power checks; validate synthesis quality and ensure smooth handoff to physical design; execute functional ECOs including conformal ECOs; build AI-driven automation flows to improve STA, synthesis, constraint creation, ECO execution, and low-power verification
Seniority
Senior, hands-on IC
