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Memory Packaging Engineer

San Jose, CA💼 Full-time🗓 2026-06-04 → 2026-07-22

Core

Lead the development of cutting-edge 2.5D/3D packaging and memory subsystem solutions for Datacenter, HPC, AI, and Automotive business units.

Role type

Senior IC memory packaging technical leader

Builds

Memory subsystems (HBM, cHBM, LPDDR, IPM) for Datacenter, HPC, AI, and Automotive applications

Domain

Semiconductor packaging and memory subsystems

Deliverable

production ML models | product features | infrastructure

Required skills

Memory roadmap development, package integration planning, supply chain management, third-party vendor management, material selection, BOM optimization, cross-functional technical coordination, project progress monitoring, manufacturing metrics analysis

Preferred skills

Strategic thinking, customer obsession, deep technical expertise in advanced packaging technologies

Technologies

HBM, cHBM, LPDDR, In Package Memory (IPM), 2.5D/3D packaging

Responsibilities

Lead memory roadmap development and package integration plan; Establish and manage relationships with memory vendors; Drive material selection and BOM optimization; Monitor and report project progress, supply chain performance, and manufacturing metrics; Collaborate with IP, ASIC design, package design, Signal Integrity, Power Integrity, Thermal, and Test Engineering teams

Seniority

Senior, hands-on IC with strategic leadership

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