Timing/EM signoff analysis engineer/technical manager
Core
Develop and maintain Timing/EM signoff criteria, methodologies, and SPICE correlations for leading process nodes and 3DIC to ensure silicon-proven timing and electromigration performance.
Role type
Senior IC physical design signoff engineer
Builds
Production silicon chips with verified timing and EM integrity
Domain
Semiconductor manufacturing, advanced process nodes, 3DIC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Timing signoff methodology, Electromigration (EM) analysis, SPICE correlation, Static Timing Analysis (STA), Synthesis/APR/EM flow expertise, Regression testing, Post-silicon data analysis
Preferred skills
Experience with leading process nodes, 3DIC architecture, Abnormal/unfixable violation resolution
Technologies
STA tools, SPICE simulators, Synthesis/APR tools, EM analysis tools
Responsibilities
Develop new signoff methodologies for chip synthesis/APR/STA/EM flows, Perform regression testing on signoff methodologies using STA violation/slack and EM results, Conduct post-silicon data analysis to validate signoff criteria
Seniority
Senior, hands-on IC
