Analog Mixed-Signal Design Verification Engineer
Core
Functional verification of analog and mixed-signal IPs including SERDES, sensors, and related interfaces.
Role type
Analog Mixed-Signal Design Verification Engineer
Builds
Robust silicon products through pre-silicon verification
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, Verilog, System Verilog, System Verilog Assertions (SVA), ASIC verification flow, test bench development, simulation, debugging, coverage closure
Preferred skills
Analog Mixed-Signal Design Fundamentals, analog behavioral modeling, power-aware simulations, gate level simulations, scripting (Unix/Linux shell, Perl, Python, Makefile), revision management (Perforce, ClearCase), C, C++, SystemC
Technologies
UVM, Verilog, System Verilog, SVA, Perforce, ClearCase
Responsibilities
Collaborate with IP design teams and other verification teams; develop test plans and configurable test benches; build test suites to meet functional and code coverage goals; support post-silicon debug
Seniority
Mid-level, hands-on IC