Staff Design Verification Engineer, HBM
Core
Verify functionality and performance of next-generation High Bandwidth Memory (HBM) and DRAM circuits for AI/ML applications, focusing on ultra-high speed designs with up to 32Gb density and 4M+ transistors.
Role type
Staff Design Verification Engineer (Mixed-Signal/Digital)
Builds
Production-ready HBM and DRAM memory products for advanced computing
Domain
Semiconductor / Memory / High Bandwidth Memory (HBM)
Deliverable
production ML models
Required skills
Mixed-signal and digital verification methodologies, SystemVerilog (SVA), full-chip and block-level verification, functional coverage development, root-cause analysis, simulation tools (HSPICE, Verilog-HDL, FINESIM), scripting (Python/Perl)
Preferred skills
Technical leadership, mentoring engineers, influencing verification strategies
Technologies
SystemVerilog, HSPICE, Verilog-HDL, FINESIM, Python, Perl
Responsibilities
Evaluate full-chip and block-level HBM/DRAM circuit designs for functional correctness and performance; Develop verification plans from functional specifications; Create and maintain verification environments, testbenches, and test vectors; Increase functional coverage across DRAM architectures; Debug design issues and drive coverage closure; Apply mixed-signal and digital verification techniques; Lead verification efforts and mentor verification engineers
Seniority
Staff, hands-on IC with leadership
