Principal DFT Engineer, HBM
Core
Designing and implementing DFT architecture for complex HBM base-die System-on-Chip (SoC) designs to ensure manufacturability and testability.
Role type
Principal SoC DFT Engineer
Builds
Testable HBM base-die SoC designs ready for tapeout and silicon bring-up
Domain
Semiconductor / Memory / Heterogeneous Integration
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (DFT flows, test architectures)
Required skills
SoC-level DFT implementation, scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, ATPG concepts, RTL-to-GDS flow integration, EDA tool proficiency (Siemens/Synopsys/Cadence), scripting (Python/Tcl/Perl)
Preferred skills
Experience with large complex SoCs involving multiple IPs, pre-silicon debug, post-silicon yield analysis
Technologies
Python, Tcl, Perl, Siemens, Synopsys, Cadence
Responsibilities
Own SoC-level DFT implementation including scan and MBIST/LBIST; Drive DFT architecture definition early in design cycle; Implement and integrate DFT logic at block, subsystem, and full-chip levels; Own DFT flow execution and signoff including lint, CDC, and coverage closure; Collaborate with physical design teams to optimize DFT for placement and timing; Partner with CAD teams to standardize DFT flows
Seniority
Principal, hands-on IC with strategy & mentorship
