Sr. Member Technical Staff - ESD and Latch-Up - HBM
Core
Define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration to solve reliability challenges.
Role type
Sr. IC Architect (ESD/Latch-Up)
Builds
High-performance memory products (HBM) with robust reliability
Domain
Semiconductor / Memory / Advanced Packaging
Required skills
ESD and latch-up design, advanced CMOS technologies (FinFET, GAA), 3D IC/TSV/die-to-die interfaces, silicon validation, system-level reliability analysis
Preferred skills
Multi-die/stacked memory system architecture, ESD device/circuit design, PDK collateral development, silicon failure debugging, cross-functional technical leadership
Technologies
FinFET, GAA, TSV, 3D IC, HBM
Responsibilities
Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects; Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging; Establish ESD/LUP standards, rule decks, and signoff criteria; Drive correlation between design assumptions, silicon validation, and field reliability; Partner with foundry and packaging teams on system-level ESD challenges
Seniority
Senior, hands-on IC
