HBM Design Engineering Lead - MTS/SMTS/DMTS
Core
Lead the design and delivery of next-generation High Bandwidth Memory (HBM) solutions for artificial intelligence and accelerated computing, guiding work from architecture definition through silicon bring-up and post-silicon support.
Role type
Senior IC HBM Design Engineering Lead
Builds
High Bandwidth Memory (HBM) subsystems and blocks for AI and high-performance computing
Domain
Semiconductor / Memory / High-Speed Interfaces
Deliverable
production ML models
Required skills
DRAM operation, JEDEC specifications, CMOS circuit design, transistor-level design, semiconductor device physics, technical project leadership, root-cause analysis, architecture definition, schematic implementation, verification, tape-out, post-silicon debug
Preferred skills
Register Transfer Level (RTL) design, analog modeling and simulation, 2.5D/3D packaging technologies, high-speed clocking and interface design, logic and custom circuit design, power delivery optimization
Technologies
Verilog, FastSpice, HSPICE
Responsibilities
Own and deliver critical HBM design blocks from architecture to post-silicon debug; Drive robust, high-performance designs balancing performance, power, reliability, yield, and manufacturability; Lead root-cause analysis of complex pre-silicon and post-silicon issues; Serve as technical project lead coordinating execution across multidisciplinary teams; Define and communicate technical strategy and execution plans; Research and influence next-generation HBM architectures; Mentor engineers through design reviews and architectural guidance
Seniority
Senior, hands-on IC with technical project leadership