3D Stacked DRAM Design Engineer
Core
Design high-speed digital IP and DRAM DFT for 3D-stacked DRAM peripheral circuits in collaboration with U.S.-based customers.
Role type
Senior IC analog/digital design engineer (3D-stacked DRAM)
Builds
3D-stacked DRAM logic dies and next-generation DRAM-on-Logic solutions
Domain
Semiconductor memory (DRAM) and digital IP
Deliverable
production ML models | product features
Required skills
RTL design to implementation, full custom + digital co-design, PDN analysis, wafer/package/system level test analysis, Python, circuit simulators (HSPICE, PrimeSim, Spectre), Virtuoso, DRAM specifications and architecture review
Preferred skills
logic foundry design experience
Technologies
Virtuoso, HSPICE, PrimeSim, Spectre
Responsibilities
Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT; Engage in foundry verification of service-ready IPs; Co-develop next-generation DRAM-on-Logic solutions with key customers
Seniority
Senior, hands-on IC