3D Stacked DRAM-on-Logic Design Engineer
Core
Design and optimize digital IP and SoC for 3D-stacked DRAM-on-Logic systems to enable advanced memory solutions for customers.
Role type
Senior IC digital design engineer (3D DRAM-on-Logic)
Builds
Digital IP and SoC for 3D-stacked DRAM
Domain
Semiconductor / Memory / 3D Stacked DRAM
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design, Hardware Description Languages (Verilog, VHDL), memory PHY design, hard macro IP for high-speed circuits, memory controller design, memory BIST, DRAM DFT/DFD, PPA analysis and optimization, physical design
Technologies
Verilog, VHDL
Responsibilities
Develop digital logic IP/SoC based on Hardware Description Languages; Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations; Establish close technical engagement with foundry companies to build digital IP of 3D-stacked DRAM
Seniority
Senior, hands-on IC
