Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)
Core
Senior IC physical design engineer executing advanced packaging design strategy for High Bandwidth Memory (HBM) product integration.
Role type
Senior IC physical design engineer (advanced packaging)
Builds
HBM memory products with advanced packaging integration
Domain
Semiconductor manufacturing / Advanced Packaging / Memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design and layout, TSV design, DRC/LVS/ERC sign-off, TSV stress modeling, DFT structures for packaging, JEDEC HBM specifications, Power/Signal integrity, Parasitic extraction
Preferred skills
Hybrid bonding, Chiplet architecture, HBM assembly processes, Layout automation scripting, Reliability physics
Technologies
Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler
Responsibilities
Build and tapeout PWF Reticles Design, Develop DFTs in test vehicles for packaging fail modes, Coordinate with design teams to build test structures for live die, Manage design rules for PWF, wafer thinning, and dicing, Engage with FE Integration teams for BEOL design, Capture Advanced Packaging requirements with Scribe Design team, Perform Electrical Simulations to understand fail mode mechanisms
Seniority
Senior, hands-on IC