Senior IC Packaging Engineer
Core
Define and drive high-performance, low-power packaging architectures for advanced IC and System-in-Package (SiP) products, leading efforts from early technology path finding through production ramp.
Role type
Senior IC Packaging Engineer (System-in-Package & Chiplet Architect)
Builds
Advanced IC and SiP packages for high-speed SerDes/PHY interfaces (PCIe, CXL, LPDDR5, UCIe)
Domain
Semiconductor manufacturing, Advanced Packaging, High-Speed Digital Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
IC packaging architecture, Chiplet-based design, RDL and bump architecture, High-speed SerDes/PHY design, Substrate stack-up definition, DFM and yield optimization, SI/PI and thermal/mechanical trade-offs, OSAT and foundry collaboration
Preferred skills
UCIe standard implementation, Silicon interposer design, EDA tool proficiency (Cadence Allegro APD, HFSS, SIwave, Ansys), New packaging methodology development
Technologies
Cadence Allegro Package Designer, HFSS, SIwave, Ansys Designer, UCIe, PCIe Gen5, LPDDR5, RDL, Flip-Chip BGA
Responsibilities
Serve as technical authority for IC and SiP packaging across multiple products; Own package architecture and technology roadmap; Lead chiplet-based packaging strategies; Perform and guide hands-on package design and physical layout; Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines; Drive SI/PI, thermal, mechanical, and reliability trade-offs; Lead external engagement with OSATs, foundries, and key suppliers; Influence product roadmap, risk management, and investment decisions; Establish scalable design methodologies and reusable packaging flows
Seniority
Senior, hands-on IC
