Design Verification DDR Lead
Core
Develop and implement comprehensive verification plans, testbenches, and environments for HBM4/4e IP and Subsystem using SystemVerilog and UVM.
Role type
Senior IC design verification lead (HBM/DDR)
Builds
HBM4/4e IP and Subsystem
Domain
Semiconductor / Memory (HBM)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, RTL design verification, simulation, debugging, coverage analysis, technical mentoring
Preferred skills
HBM4/4e architecture knowledge, verification metrics analysis, review facilitation
Technologies
SystemVerilog, UVM
Responsibilities
Develop verification plans for HBM4/4e IP; Create and maintain testbenches and verification environments; Perform functional verification including simulation and debugging; Collaborate with design engineers on specifications; Identify and resolve design/verification issues; Generate and analyze verification metrics; Participate in design and verification reviews; Stay updated on verification technologies; Mentor junior verification engineers
Seniority
Senior, hands-on IC
