Principal Engineer - Board/Package Co-design
Core
Principal hardware architect specializing in PCB and silicon package co-design for high-performance embedded compute platforms.
Role type
Principal Engineer, System-Level Hardware Architect (PCB/Package Co-design)
Builds
Physical hardware development platforms based around custom Arm SoCs for embedded compute, Cloud/Edge AI, and IoT.
Domain
Semiconductor hardware design, embedded systems, high-speed interfaces.
Required skills
SoC architecture, high-speed IO interfaces (PCIe Gen5/6/7, LPDDR5/6), embedded board design, IC packaging technologies, escape routing analysis, Signal and Power Integrity (SI/PI), PCB fabrication processes (HDI, stackup), EDA tools (Cadence OrCAD & Allegro), component placement, PDN strategy.
Preferred skills
Signal Integrity tools (ANSYS, Siemens EDA), compute architectures, semiconductor industry experience.
Technologies
Cadence OrCAD, Cadence Allegro, ANSYS, Siemens EDA, PCIe, LPDDR, FPGAs, PMICs.
Responsibilities
Collaborate with SoC teams to define technical requirements and align features; drive PCB development alongside chip packaging teams; evaluate package pinout options against PCB routability and SI/PI performance; support early silicon and board architecture definition including form-factor constraints and routing feasibility; provide timescale estimates and justifications to the program team. (via careerplan.io/jobs/99030822768-principal-engineer-boardpackage-co-design-at-arm)
Seniority
Principal, hands-on IC with strategy & mentorship