Senior Mask Layout Design Engineer
Core
Perform physical layout for high-speed mixed-signal circuits (PLLs, I/O, ESD) in sub-micron CMOS technologies for VLSI products.
Role type
Senior IC mask layout design engineer
Builds
Custom layouts for ASIC and mixed-signal integration
Domain
Semiconductor manufacturing / Analog & Mixed-Signal IC design
Required skills
FinFET tape-out, Cadence Virtuoso, DRC/LVS verification, submicron CMOS analog layout, high-speed SerDes/RF layout, Perl/Python scripting
Preferred skills
TSMC N5/N4/N3 process, top-level integration, ICV/Calibre tools
Technologies
Cadence Virtuoso, ICV, Calibre, Perl, Python, TSMC N5/N4/N3
Responsibilities
Perform physical layout for mixed-signal functions; customize designs for integration; verify layouts against design rules and schematics
Seniority
Senior, hands-on IC
