Senior Full Chip Layout Engineer
Core
Full-chip physical design and verification for high-speed networking silicon devices.
Role type
Senior Full Chip Layout Engineer (Physical Design)
Builds
High-throughput, low-latency networking chips
Domain
Semiconductor / Networking Silicon
Deliverable
production ML models | product features
Required skills
Full-chip layout, Physical Verification (DRC, LVS, ANT, ERC, DFM), Floorplanning, Pinning, Bump routing, TCL scripting, Unix/Shell scripting, Linux environment usage, EDA tools (Synopsys ICC2/FC, Cadence Innovus, Synopsys ICV, Siemens Calibre)
Preferred skills
Methodology definition, Flow ownership, Place and Route expertise
Technologies
Synopsys ICC2/FC, Cadence Innovus, Synopsys ICV, Siemens Calibre, TCL, Unix, Shell
Responsibilities
Perform physical layout for full-chip level, integration, pinning, and bump routing; Collaborate with block owners and project managers to ensure high-quality convergence; Manage chip layout from floorplanning through tape-out.
Seniority
Senior, hands-on IC
