Senior Mask Layout Design Engineer
Core
Perform physical layout for mixed-signal functions (PLLs, high-speed I/O, ESD structures) in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer
Builds
VLSI products integrating mixed-signal and ASIC designs
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed-signal circuit layout, Sub-micron CMOS technology, Cadence Virtuoso, DRC/LVS verification, Perl/Python scripting, Floor planning
Preferred skills
Custom DRC/LVS deck creation, Debugging layout verification flows
Technologies
Cadence Virtuoso, Dracula, Hercules, Calibre, Primeyield, Perl, Python
Responsibilities
Perform physical layout for mixed-signal functions, Work with ASIC and mixed-signal engineers to customize designs, Execute floor planning and custom layout, Verify designs against rules and schematics
Seniority
Senior, hands-on IC
