Physical Design STA Engineer
Core
Developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
Role type
Senior IC physical design STA engineer
Builds
Networking chips and SOCs
Domain
Semiconductor / Networking Silicon
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical Design, Static Timing Analysis (STA), Timing closure methodologies, Power Integrity, IR-drop analysis, Electromigration (EM) analysis, Back-end verification, Tcl/Perl/Python scripting
Preferred skills
Signoff domains (PrimeTime, PrimePower, RedHawk, Formality), Backend CAD, Versatility
Technologies
PrimeTime, PrimePower, RedHawk, Formality
Responsibilities
Develop physical design and STA flows for networking chips; Collaborate with block owners and full Chip STA engineers for convergence; Create solutions for state-of-the-art physical design problems; Develop flow and tool methodologies for timing, power, and noise analysis.
Seniority
Mid-level, hands-on IC
