Senior Physical Design and Timing Engineer
Core
Drive physical design and timing of high-frequency, low-power NVIDIA CPUs, GPUs, LPUs, and SoCs from RTL to tapeout.
Role type
Senior IC physical design and timing engineer
Builds
High-performance CPUs, GPUs, LPUs, and SoCs for AI computing, gaming, and accelerated computing
Domain
Semiconductor hardware design (CPU/GPU/SoC)
Deliverable
production ML models | product features
Required skills
Static Timing Analysis, timing-constraint development, multi-mode multi-corner timing closure, logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, ECO implementation, Python/Tcl/Perl scripting, AI/ML/DL/LLMs knowledge
Preferred skills
High-performance CPU/GPU/AI accelerator physical design, advanced physical design & circuits optimizations, clocking strategies, timing-closure strategies, scalable optimization automation, AI/Agentic framework development
Technologies
EDA tools, Python, Tcl, Perl, Make
Responsibilities
Drive physical design and timing at block, cluster, and full chip levels; Implement frontend and backend flows including synthesis, equivalence checking, and power/performance/area optimization; Collaborate in cross-functional environments
Seniority
Senior, hands-on IC
