Senior ASIC Verification Engineer
Core
Design and maintain unit-level/sub-system verification environments for system-level IP, focusing on verifying and improving methodologies for high-quality, robust designs across multiple environment levels.
Role type
Senior IC ASIC Verification Engineer
Builds
System-level IP for NVIDIA GPUs and AI chips
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, OOPs-based programming, Python, RTL design (Verilog), computer architecture fundamentals, verification tools (VCS, Verdi)
Preferred skills
Experience with automation of build/regression/triage, latest verification techniques
Technologies
System Verilog, UVM, Python, Verilog, VCS, Verdi
Responsibilities
Design and maintain unit level/sub-system Verification environment; Develop and carry out test plans to verify design; Create UVM components, sequences, tests and scoreboards; Sign off on verification efforts with high-quality code and functional coverage; Launch regressions, resolve issues, and achieve DV milestone targets; Automate manual steps in build, regression, and triage; Collaborate with architects, designers, and software engineers; Ensure end-to-end verification of IPs
Seniority
Senior, hands-on IC
