SENIOR ENGINEER HBM LAYOUT
Core
Senior IC layout engineer developing analog, mixed-signal, and custom digital blocks for High Bandwidth Memory (HBM) technologies used in AI and high-performance computing.
Role type
Senior IC layout engineer (analog/mixed-signal/custom digital)
Builds
Analog, mixed-signal, and custom digital blocks for HBM chips
Domain
Semiconductor / Memory / AI Hardware
Required skills
Analog layout development, Mixed-signal layout, Custom digital layout, Full-chip integration, LVS/DRC/Antenna verification, Cadence VLE/VXL, Mentor Calibre DRC/LVS, Temperature Sensor layout, PLL layout, ADC/DAC layout, LDO layout, Bandgap layout, Reference Generator layout, Charge Pump layout, Current Mirror layout, Comparator layout, Differential Amplifier layout, Analog Layout fundamentals (Matching, EM, Latch-up, Coupling, Crosstalk, IR-drop), Parasitic device management, Build constraint implementation
Preferred skills
Tape-out management, Multi-project layout management, Physical verification problem-solving
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Build and develop analog, mixed-signal, and custom digital blocks; Perform layout verification tasks (LVS/DRC/Antenna checks); Lead planning, area/time estimation, scheduling, and execution; Communicate with global engineering teams; Apply AI-enabled methodologies for automation.
Seniority
Senior, hands-on IC
