Engineer, Advanced Packaging Development - Design Enablement & Layout
Core
Develop design rules, requirements, and test structures for advanced packaging; create layout and DBR test vehicle designs to support technology development.
Role type
Senior IC advanced packaging design engineer
Builds
Advanced packaging test vehicles and product layouts
Domain
Semiconductor memory and storage / Advanced packaging
Required skills
Semiconductor memory process flows, TSV based packaging, EDA tools (Cadence Virtuoso, Calibre, Hspice), Design Rule Characterization, Python/R/MATLAB programming, Data analysis
Preferred skills
SKILL or SVRF coding, AI Agentic Workflow, AI tool usage in layout design
Technologies
Cadence Virtuoso, Calibre, Hspice, Python, R, MATLAB
Responsibilities
Develop and refine Design Rules, Requirements, and Test Structures for advanced packaging; Create layout and DBR test vehicle and product designs; Ensure robust Design Rule Checks (DRC) and respond to deviations; Analyze large datasets to extract insights; Leverage AI to reduce development time; Manage structure evaluation to quantify process margins; Partner with teams to resolve layout-related process issues; Document and communicate complex problem resolutions.
Seniority
Mid-level, hands-on IC
