New College Grad - Engineer, ASIC Digital Design
Core
Design and develop RTL for next-generation DRAM memory controllers and subsystems using SystemVerilog, supporting simulation, validation, and chip bring-up.
Role type
Junior IC ASIC Digital Design Engineer
Builds
High-performance, production-ready silicon for future DRAM products
Domain
Semiconductor / Memory / Digital Logic
Deliverable
production ML models | product features
Required skills
SystemVerilog, RTL design, digital logic design, HDL modeling, simulation and co-simulation, Python scripting, Linux Shell, basic analog/mixed-signal concepts (PLLs, DLLs, CDRs, CMOS)
Preferred skills
DRAM interface design, memory controller design, ASIC development tools (synthesis, linting, formal verification), silicon bring-up debugging, automation solution development
Technologies
SystemVerilog, Python, Linux Shell, AI-enabled tools (Copilot, Claude)
Responsibilities
Design and develop RTL for DRAM memory controllers; Collaborate with analog, verification, and physical design teams; Develop and validate HDL models; Support chip bring-up and debugging; Use scripting and AI tools to improve design workflows
Seniority
Entry-level (0-2 years experience)
