Sr Principal ASIC / RTL Design Engineer
Core
Design, integrate, and verify memory subsystems (SRAM, ROM, EEPROM, OTP/NVM) within advanced SoC platforms.
Role type
Senior Principal ASIC / RTL Design Engineer
Builds
Advanced SoC platforms with integrated memory subsystems
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design (Verilog/SystemVerilog), memory IP integration (SRAM, ROM, EEPROM, OTP/NVM), EDA tools for synthesis/lint/static timing analysis, CDC analysis, design verification planning, post-silicon debug
Preferred skills
Mentoring junior engineers, architecture discussions, documentation of design flows
Technologies
Verilog, SystemVerilog, EDA tools
Responsibilities
Own and drive integration of memory IPs into larger digital subsystems and SoC platforms; Collaborate with memory IP teams to understand interface requirements, timing constraints, and test features; Perform RTL design, lint, CDC, and synthesis for digital logic blocks interacting with embedded memories; Define and execute design verification plans in coordination with the verification team; Interface with physical design and validation teams to ensure successful implementation and bring-up; Support post-silicon debug for memory interface-related issues
Seniority
Senior, hands-on IC
